This invention relates to a semiconductor device and manufacturing process, and more particularly, to an improved DRAM device utilizing vertically oriented access transistors and its manufacturing method.
A semiconductor memory device comprises of millions of memory cells tightly packed in an array on a semiconductor substrate. Each of the memory cells typically includes an access transistor and a storage capacitor, and the cells are accessed using word lines and bit lines. In order to increase the density of the memory cells, the footprint of each memory cell must decrease. One difficulty in reducing the area of a memory cell is that when the surface area of the capacitor storage nodes become too small, the capacitor cannot store a sufficient amount of electric charge to overcome leakage current, resulting in data loss. In the past, various ways have been proposed to pack the transistor and storage capacitor in a very small area. One method is to use stacked crown capacitors, so that the footprint of the capacitor is reduced, while the surface area of the storage nodes of the capacitor remains substantially the same. Another method is to use vertical trench capacitors that bury deep into the substrate, so that the capacitor occupies a small area on the substrate, yet its storage node has enough surface area to retain sufficient electric charge. Typically, a horizontal transistor is coupled to the trench capacitor. Methods have been proposed to stack a vertical transistor on top of the trench capacitor, but the methods for forming such a device has been complex and expensive.
The present invention is directed to an improved DRAM cell having high density that can be manufactured using simple processing steps.
A vertical-transistor trench-capacitor memory cell and method of making such memory cell is provided. A memory cell includes a transistor and a capacitor formed along the sidewall of a trench that is formed below the crossing of a word line and a bit line. The capacitor is formed in the lower portion of the trench, and the source and drain regions of the transistor are formed in the substrate adjacent to the upper sidewall of the trench. The source is formed by thermal diffusion, and the drain is formed by ion-implantation. The gate electrode is formed within the upper portion of the trench, separated from the capacitor by an insulating layer. The gate electrode is connected to a word line via a gate contact window, and the drain region is connected to a bit line via a drain contact window. The drain region of one memory cell is extended and connects to the drain region of an adjacent memory cell. The two cells share a common drain contact window, and are surrounded by an isolation layer.